IC package substrate thermal expansion testing measures the coefficient of thermal expansion (CTE) of packaging substrates to prevent warpage, delamination, and solder joint failure in BGA, CSP, and flip-chip devices. Using techniques such as thermomechanical analysis (TMA) and dilatometry, laboratories determine in-plane and Z-axis CTE, glass transition temperature, and thermal shrinkage in accordance with ASTM and IPC standards. This guide explains sample types, testing items, measurement methods, industrial applications, and frequently asked questions related to IC package substrate thermal expansion evaluation.
Technical Overview
IC package substrates provide the essential electrical, thermal, and mechanical interconnection between the silicon die and the printed circuit board. Because the substrate is sandwiched between materials with very different thermal expansion behaviors—single-crystal silicon at approximately 2.6 ppm/°C and typical PCB laminates at 14–17 ppm/°C—its coefficient of thermal expansion (CTE) must be tightly controlled and accurately verified. When the substrate CTE deviates from the design window, thermomechanical stress accumulates during reflow soldering, power cycling, and long-term field operation, resulting in solder joint fatigue, interfacial delamination, copper trace cracking, and excessive package warpage.
Thermal expansion testing quantifies the dimensional change of the substrate as a function of temperature. The resulting data deliver the alpha 1 CTE (below the glass transition temperature), alpha 2 CTE (above the glass transition temperature), glass transition temperature (Tg), and permanent thermal shrinkage after excursions to reflow-level temperatures. These parameters are fundamental inputs for finite element simulation, design rule definition, material selection, and reliability qualification of substrates used in ball grid array (BGA), land grid array (LGA), chip scale package (CSP), and flip-chip (FCBGA) packages.
Testing Samples
Organic Laminate Package Substrates
Bismaleimide triazine (BT) resin and epoxy-glass substrates used in BGA, QFN, and memory packages. These samples are typically tested in both the in-plane (X/Y) direction and the Z-axis direction to capture anisotropic expansion behavior.
Build-Up Film Substrates
Substrates based on Ajinomoto Build-up Film (ABF) or similar dielectric build-up layers, widely used for high-density flip-chip packages in CPUs, GPUs, and networking devices. Testing focuses on the CTE of the build-up layers and the composite structure after full lamination and curing.
Ceramic and Special Substrates
Alumina, aluminum nitride, and low-temperature co-fired ceramic (LTCC) substrates, as well as silicon interposers for 2.5D/3D packaging. These low-CTE materials require high-resolution measurement techniques such as dilatometry or interferometry.
Material-Level Specimens
Copper-clad laminates, core materials, prepreg sheets, and free-standing dielectric films submitted for incoming material qualification or new supplier approval before substrate fabrication.
Testing Items
Thermal expansion evaluation of IC package substrates typically covers the following parameters:
- In-plane (X/Y) coefficient of thermal expansion below the glass transition temperature (alpha 1 CTE)
- In-plane (X/Y) coefficient of thermal expansion above the glass transition temperature (alpha 2 CTE)
- Z-axis (out-of-plane) CTE, which drives plated via and interconnect stress
- Glass transition temperature (Tg) determined from the inflection point of the expansion curve
- Permanent thermal shrinkage or irreversible dimensional change after heating to reflow peak temperatures
- CTE hysteresis and expansion behavior across repeated thermal cycles
- Package-level warpage or thermal bow measured over the reflow temperature profile
Testing Methods
Thermomechanical Analysis (TMA)
TMA is the most widely used method for substrate CTE measurement. A specimen of controlled dimensions is placed under a low-force expansion probe and heated at a standard rate (typically 5 °C/min or 10 °C/min) under nitrogen purge, while a high-resolution displacement sensor records dimensional change. Commonly applied standards include ASTM E831 for solid materials and IPC-TM-650 Method 2.4.24 for Z-axis thermal expansion and Tg of printed boards and substrates. Test temperatures commonly span from room temperature or −55 °C up to 260 °C to simulate assembly and operating conditions.
Push-Rod Dilatometry
Horizontal or vertical dilatometers per ASTM E228 provide excellent accuracy for low-expansion ceramics, interposers, and reference materials. The method measures bulk linear expansion over a wide temperature range and is often used to cross-verify TMA results or calibrate reference standards.
Optical and Full-Field Methods
Digital image correlation (DIC) and shadow moiré interferometry measure full-field in-plane strain and out-of-plane warpage across an entire substrate or assembled package. Shadow moiré testing aligned with JEDEC JESD22-B112 characterizes dynamic warpage during simulated reflow profiles, which is critical for BGA and LGA coplanarity control.
Strain Gauge Method
Bonded high-temperature strain gauges measure in-plane CTE of fully processed substrates or assembled packages under realistic thermal cycling conditions, capturing the effective composite behavior rather than that of a coupon alone.
Typical Test Conditions
- Temperature range: −55 °C to 260 °C (or tailored to the application profile)
- Heating rate: 5 °C/min or 10 °C/min under nitrogen atmosphere
- Specimen conditioning: bake-out to remove moisture before measurement
- Reported outputs: alpha 1, alpha 2, Tg, expansion curve, and total displacement versus temperature
Applications
Thermal expansion testing data for IC package substrates support multiple engineering and quality functions across the electronics supply chain:
- Package design and simulation: Providing accurate CTE inputs for thermomechanical finite element models to predict solder joint stress and warpage before tape-out.
- Material qualification: Comparing candidate core materials, prepregs, and build-up films against design targets such as an in-plane CTE of 10–17 ppm/°C matched to the board.
- Supplier and incoming inspection: Verifying lot-to-lot consistency of substrate CTE and Tg for fabricators and OSAT providers.
- Reliability qualification: Supporting temperature cycling assessments per JEDEC JESD22-A104 and automotive requirements such as AEC-Q100 Grade 0 and Grade 1.
- Failure analysis: Identifying CTE drift or degradation after moisture absorption, rework, or thermal aging when investigating delamination, cracking, or open solder joints.
- Process optimization: Evaluating the influence of lamination pressure, curing schedule, and copper density on final substrate dimensional stability.
FAQ
What is a typical CTE value for an IC package substrate?
Most organic package substrates are engineered to an in-plane CTE of approximately 10–17 ppm/°C below Tg to bridge the gap between silicon (about 2.6 ppm/°C) and standard PCB laminates (about 14–17 ppm/°C). Ceramic substrates range from about 4 to 7 ppm/°C, while Z-axis CTE of organic substrates can reach 40–80 ppm/°C or higher above Tg.
Why are alpha 1 and alpha 2 CTE both reported?
Organic substrate materials expand linearly below the glass transition temperature (alpha 1) but expand at a much higher rate once the polymer matrix softens above Tg (alpha 2). Because reflow soldering exposes the package to temperatures well above Tg, alpha 2 is often the limiting value for reliability, so both figures are required for design and qualification.
What standards govern substrate thermal expansion testing?
Commonly referenced standards include ASTM E831 (TMA), ASTM E228 (dilatometry), IPC-TM-650 Method 2.4.24 (Z-axis expansion and Tg of printed boards), and JEDEC JESD22-B112 (package warpage measurement). Specific product specifications may define additional conditions.
How should samples be prepared for accurate results?
Specimens must be flat, free of cracks and burrs, and conditioned to remove absorbed moisture, since humidity can distort expansion curves. Minimum dimensions are defined by the test method, and the measurement direction relative to the substrate weave or rolling direction must be documented because substrate CTE is anisotropic.
TMA or dilatometry—which method should be chosen?
TMA offers fast turnaround, small sample size, and simultaneous Tg determination, making it the default choice for organic substrates. Dilatometry provides higher absolute accuracy for very low CTE materials such as ceramics and silicon interposers. For assembled packages or full-field warpage behavior, optical methods such as shadow moiré or DIC are recommended.