The in-plane coefficient of thermal expansion (CTE) of a semiconductor packaging substrate is a decisive parameter that governs solder joint reliability, package warpage, and delamination resistance in integrated circuit assemblies. This article provides a professional technical overview of in-plane CTE determination for IC substrates, covering applicable standards such as ASTM E831, ASTM E228, ISO 11359, IPC-TM-650, and JIS K 7197, together with sample preparation, measurement procedures, data reduction, and typical engineering applications. It is intended for materials engineers, packaging designers, and quality professionals involved in substrate qualification and reliability assessment.
Technical Overview
The coefficient of thermal expansion (CTE) describes the fractional change in length of a material per unit change in temperature, typically expressed in ppm/°C (10⁻⁶/K). For a semiconductor packaging substrate, the in-plane (X–Y) CTE, denoted αx and αy, is of particular engineering importance because the substrate sits between a silicon die with a CTE of approximately 2.6 ppm/°C and a printed circuit board or mold compound with substantially higher expansion. Mismatched in-plane expansion during reflow, thermal cycling, and power cycling generates thermomechanical stress that drives solder joint fatigue, underfill delamination, thin-film cracking, and excessive package warpage.
Packaging substrates are structurally anisotropic. Woven glass fabric reinforcement constrains expansion in the X and Y directions, while the resin-rich Z axis expands much more aggressively, particularly above the glass transition temperature (Tg). For this reason, the in-plane CTE must be evaluated independently along two orthogonal directions, usually the machine direction (MD) and cross direction (CMD), or along defined substrate X/Y axes. The measured behavior is conventionally reported as two values: α1 below Tg and α2 above Tg, together with the dilatometric Tg obtained from the inflection of the expansion curve.
Typical in-plane CTE values below Tg include approximately 10–15 ppm/°C for bismaleimide triazine (BT) laminates, 12–17 ppm/°C for glass-fabric epoxy systems, 15–25 ppm/°C for build-up dielectric layers, 6–7 ppm/°C for alumina ceramic substrates, and 4–5 ppm/°C for aluminum nitride. Accurate determination of these values is essential for material qualification, finite-element warpage simulation, and compliance with specification limits such as those defined in IPC-4101 slash sheets.
Testing Samples
Organic Laminate Substrates (BT, Epoxy-Glass, ABF Build-Up)
Coupons are cut from production panels or finished substrates, typically 6–10 mm in length and 2–4 mm in width, with a thickness between 0.1 mm and 1.5 mm. Specimens are prepared in pairs aligned with the two orthogonal in-plane axes so that directional anisotropy can be quantified. When the objective is to characterize the laminate itself, copper foil and patterned traces are removed by chemical etching prior to cutting; when the objective is product-level behavior, the specimen is tested as fabricated.
Ceramic Substrates (Alumina, Aluminum Nitride, LTCC/HTCC)
Rigid ceramic coupons are prepared with ground and lapped end faces to ensure parallelism within tight tolerance, as required for push-rod dilatometry. Specimen lengths of 10–25 mm are commonly used, and the low CTE of these materials demands high-resolution instrumentation or interferometric techniques.
Sample Preparation and Conditioning
- Cut edges must be straight, parallel, and free of chips, cracks, and delamination induced by the cutting process.
- Moisture-sensitive organic substrates are baked (typically 105 °C for 1–2 h) or vacuum-dried, then conditioned at 23 ± 2 °C and 50 ± 5% relative humidity in accordance with ISO 291 or IPC-TM-650 conditioning requirements.
- Thickness and gauge length are measured with calibrated instruments (micrometer or optical measurement system) at the conditioning temperature before testing.
- A minimum of three specimens per in-plane direction is recommended to characterize scatter arising from glass-weave distribution and resin content variation.
Testing Items
The standard scope of a planar expansion characterization program for packaging substrates includes the following measurable quantities:
- In-plane CTE below the glass transition temperature (α1, ppm/°C) for both X/Y or MD/CMD directions.
- In-plane CTE above the glass transition temperature (α2, ppm/°C), where resin softening substantially increases expansion.
- Dilatometric glass transition temperature (Tg) determined from the inflection point of the dimension-versus-temperature curve.
- Total percent linear expansion across a defined temperature window, for example 30 °C to 260 °C, which spans the lead-free reflow profile.
- In-plane anisotropy ratio (αx/αy), used to assess weave balance and lamination symmetry.
- Through-thickness (Z-axis) CTE as a complementary measurement where full anisotropic material models are required.
Testing Methods
Thermomechanical Analysis (TMA)
TMA is the predominant method for organic packaging substrates and is performed in accordance with ASTM E831, ISO 11359-2, IPC-TM-650, and JIS K 7197. The specimen is placed in the furnace with a low-mass expansion probe applying a static force of approximately 0.02–0.1 N, heated at a controlled rate of 5 °C/min under nitrogen purge (20–50 mL/min), and subjected to a programmed temperature range such as 25–300 °C. For in-plane measurement, the coupon is oriented so the probe senses length change along the specimen axis, or a dedicated in-plane fixture is used. Calibration against reference materials (sapphire, aluminum) is mandatory before testing. A heat–cool–heat sequence is frequently applied, with data reported from the second heating cycle to erase free-volume and stress-relaxation artifacts from processing.
Push-Rod Dilatometry
Vitreous silica push-rod dilatometry per ASTM E228 is well suited to rigid substrates, ceramics, and larger coupons. The specimen is heated in a calibrated furnace and its dimensional change is transmitted through a low-expansion fused-silica rod to a precision displacement sensor. The method offers excellent accuracy for CTE values above roughly 2 ppm/°C and provides robust α1/α2 results when combined with slow, controlled heating rates of 3–5 °C/min.
Interferometric and Optical Methods
For low-CTE ceramics, silicon interposers, or applications demanding the highest precision, absolute interferometric dilatometry per ASTM E289 provides resolution in the nanometer range. Full-field optical techniques, including digital image correlation (DIC) and shadow moiré interferometry, extend in-plane strain measurement to whole substrate panels and enable simultaneous warpage mapping, which is valuable for correlating local expansion with package-level deformation behavior.
Data Reduction and Calculation
The mean linear CTE between two temperatures is calculated as α = (1/L0) × (ΔL/ΔT), where L0 is the initial gauge length, ΔL is the dimensional change, and ΔT is the temperature interval, with the result expressed in ppm/°C. The expansion curve is fitted piecewise: α1 is derived by linear regression over the window below Tg (for example 50–150 °C), and α2 over the window above Tg (for example Tg + 30 °C to Tg + 80 °C), while the dilatometric Tg is taken as the intersection of the two regression lines. Reported results include individual values, mean, standard deviation, test direction, temperature range, heating rate, and thermal history.
Applications
Determination of substrate in-plane CTE supports multiple stages of semiconductor package development and manufacturing:
- Qualification of IC substrates for flip-chip packages, ball grid arrays, flip-chip chip-scale packages, and system-in-package modules, where die-substrate CTE mismatch directly controls solder bump and ball joint reliability.
- Input material data for warpage simulation and finite-element thermomechanical modeling used to predict coplanarity during reflow assembly.
- Selection and verification of matching underfill, mold compound, and adhesive systems to minimize interfacial stress across the operating temperature range.
- Risk assessment for reflow-induced defects, including popcorn cracking, delamination, and copper trace fracture in thermally cycled molded packages.
- Incoming inspection and lot acceptance of laminate, prepreg, and build-up film materials against IPC-4101 and customer-specific specification limits.
- Research and development of next-generation low-expansion dielectrics, low-loss glass fabrics, and ceramic substrate formulations for high-density and high-power packaging.
- Independent verification testing by accredited third-party laboratories operating under ISO/IEC 17025 quality systems for customer audits and failure analysis programs.
FAQ
Q: Why is in-plane CTE measured instead of a single bulk value?
A: Because substrates are reinforced with woven glass fiber or ceramic fillers, expansion is strongly directional. The X and Y directions are constrained by the fiber network and must match the silicon die, while the Z direction is resin-dominated and expands several times more, especially above Tg. Only directional measurement provides data usable for reliability engineering.
Q: What are typical acceptance values for in-plane CTE?
A: For organic flip-chip substrates, an in-plane α1 of approximately 10–17 ppm/°C is common, striking a compromise between the silicon die (~2.6 ppm/°C) and the application board (~14–17 ppm/°C). Ceramic substrates typically fall between 4 and 8 ppm/°C. Exact limits are set by package design rules and the applicable material specification.
Q: Over what temperature range should the measurement be made?
A: The range must bracket the actual thermal excursions of the package. A common program is 25 °C to 260 °C to cover lead-free reflow, with α1 and α2 reported separately and the dilatometric Tg identified at the curve inflection.
Q: How does copper circuitry affect the result?
A: Patterned copper (~17 ppm/°C) modifies the effective composite expansion of the finished substrate. Characterization tests on copper-free laminate evaluate the base material, while tests on as-fabricated panels evaluate the real product stack-up. Both data sets are frequently required for accurate simulation.
Q: What accuracy can be expected?
A: Properly calibrated TMA and dilatometry systems typically achieve repeatability within ±2–5% or ±0.5 ppm/°C, whichever is greater, for organic substrates. Interferometric methods provide superior precision and are preferred for very low expansion materials.
Q: Which standards govern the test?
A: Primary references include ASTM E831 (TMA), ASTM E228 (dilatometry), ASTM E289 (interferometry), ISO 11359-1 and ISO 11359-2 (thermomechanical analysis of plastics), IPC-TM-650 test methods for printed board materials, IPC-4101 specification limits, and JIS K 7197, with ISO/IEC 17025 governing laboratory competence.